The Department of Electronics and Communication Engineering in association with The Institution of Telecommunication Engineers (IETE) organised a hands-on training titled “Practical Verilog HDL using Xilinx Vivado and EDA Playground” on February 12, 2026 at Cute Hall and Networks Laboratory. The training was aimed at providing participants with practical exposure to Hardware Description Language (Verilog HDL) design, simulation, verification, and implementation using industry-standard tools such as Xilinx Vivado and EDA Playground.
The event began with a Prayer Song by the students, followed by the presentation of the Vision, Mission, PEO of the department by Ms.S.Sasipoorani of III-year ECE. The Welcome Address was delivered by Mr.Madhavan B G of II-year ECE. Prof. Kamala Krishnamurthy, PIF, Centre Head Paavai Educational Institutions, delivered the Presidential Address, who emphasized the significance of Verilog HDL in digital system design and its applications in modern VLSI / FPGA engineering. She encouraged participants to actively engage in hands-on activities and highlighted the importance of mastering both simulation and synthesis workflows for future academic and industry roles. The overview of the hands-on training was delivered by Ms.Dharanya.K of II ECE.
The training sessions were handled by Mr.S.Vijay Murugan, Assistant Professor, Department of Electronics and Communication Engineering, Paavai Engineering College, who demonstrated Verilog design examples, explained simulation techniques and guided participants through hands-on exercises. He highlighted the best practices for writing Verilog code, testing and simulation workflows using Xilinx Vivado.
During the training, participants learned the features of the Xilinx Vivado IDE, including project setup, module creation, testbench development, synthesis, and implementation. Finally, the training covered real-time applications of Verilog HDL in digital design such as combinational Circuit, 8-Bit Adder and Arithmetic and Logic Unit. Through EDA Playground, attendees gained hands-on experience in writing Verilog code, running simulations, and interpreting waveform outputs. The interactive format enabled participants to clarify doubts and apply theoretical concepts directly to practical design tasks.
The success of the event was supported significantly by the faculty and student coordinators, under the guidance of Convener Dr. R. Mohanapriya, HoD,ECE, Paavai Engineering College, who oversaw the overall planning and execution of the training program. Faculty coordinators Mr.S.Vijay Murugan, Mr.S.Loganathan, Mrs.L.Sujitha, Mrs.A.Sujitha, Mr.DSatheesh Kumar and Mrs.A.Aarthi played key roles in organizing the sessions, coordinating logistics, preparing the lab environment, and guiding participants throughout the hands-on exercises. 57 students from various colleges attended the training session and participation certificates were distributed. Student coordinators Kannan K S and Surendar S from third year ECE, actively assisted with participant registration, setup of software tools in the laboratory, and supporting attendees during workshop activities. Their combined efforts ensured smooth execution of all activities and helped maintain a productive and engaging learning environment.
